Teseda's silicon validation and analysis solutions
exploit the full power of DFT, uniting Design, Test, Inspection,
FA and Manufacturing to cut weeks from time-to-market and improve device
yield and profitability. Visit this page frequently for updates and
news regarding Teseda, including press releases and white papers. Also
see our company
background information.
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Teradyne and Teseda Providing Time-to-Market
and Yield Enhancement Solutions for the UltraFLEX and J750 Test Platforms
NORTH READING, MA – October 28, 2008 – Teradyne (NYSE: TER) today announced their
decision to collaborate with Teseda on an integration of the IG-XL™ programming
environment with Teseda’s Diagnostic Manager Series toolset and WorkBench™ (TWB)
software. As a result, customers will achieve an expanded capability to perform
silicon debug, failure analysis and yield learning on Teradyne test platforms
with a resulting decrease in time-to-market and improvement in profitability.
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Teseda and Mentor Graphics Partner to Speed Defect Diagnosis
PORTLAND, Oregon ─ October 24, 2008─Teseda Corporation, a leading silicon
validation and failure analysis diagnostic company, announced today that they
have partnered with Mentor Graphics to link Mentor Graphic’s YieldAssist toolset
with the Teseda Diagnostic Environment. This new capability will provide
Teseda and Mentor customers with an integrated and truly layout-aware roundtrip
flow that will accelerate their ability to rapidly diagnose scan failures down
to the yield-limiting defects, and identify those defects in the physical layout. The
portability and low cost of the Teseda platform will allow more users access
to the new iterative diagnosis capability in YieldAssist. Coupled with
the massive failure capture memory in the Teseda V-series systems, the YieldAssist
tool will be able to iterate on even the most data-intensive defect candidates,
such as defects in the scan logic.
The Teseda TWB Software will process test patterns from Mentor Graphics
ATPG tools and run them directly on any Teseda TWB supported platforms,
including the V520 and V550. The failure files are then passed to YieldAssist
to analyze the test response and identify defect candidates. The resulting
defect candidates can then be shown in the Teseda NetXY physical viewing
environment. Optionally, the YieldAssist tool may be instructed to further
isolate the candidates down to the most probable defect(s) by producing
an iterative pattern set which can be immediately applied to the device-under-test
though the Teseda Platform. This iterative process will yield the most
probable defect candidate(s), which again may be highlighted in Teseda’s
NetXY physical viewing environment.
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NVIDIA adopts Teseda’s V550™ Debug & Diagnostic
platform
Takes delivery of initial Silicon Validation and FA diagnostic
platform
PORTLAND, OR-June 24, 2008 – Teseda Corporation, a leading provider of comprehensive
scan-based diagnostic and debug solutions for semiconductor yield improvement,
announced today that NVIDIA has taken delivery of their first V550™ system, and
will be acquiring multiple systems. The V550™ is part of a unified system that
integrates design, test, and diagnostic environments, leading to the rapid detection
and repair of failures. The V550™ is the most powerful desktop validation platform
in the industry, able to handle devices with up to 512 channels and providing
more memory per channel than any other desktop system. When driven with Teseda’s
powerful TWB™ software, it allows design teams to cut validation and diagnostic
time, and FA teams to quickly pinpoint failure candidates.
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Teseda Corporation Adds KT Venture Group, LLC
to Investors
PORTLAND, Oregon ─ May 14, 2008─Teseda Corporation, a leading silicon validation
and failure analysis company, has closed a new investment round. This most recent
round featured the addition of strategic investor KT Venture Group, LLC, the
investment partner of KLA-Tencor Corporation (NASDAQ: KLAC). Existing investors
PacRim Venture Partners and SmartForest Ventures also participated in this round.
The new funds will be used to grow the field organization and accelerate deployment
of the Diagnostic Manager Series of yield-enhancing tools.
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Hamamatsu Photonics adopts
Teseda Platforms for Failure Analysis Systems
PORTLAND, OR-October 24, 2007 – Teseda Corporation, a leading provider
of comprehensive scan-based diagnostic and debug solutions for semiconductor
yield improvement, announced that Hamamatsu Photonics K.K will adopt
its V-series hardware DFT test platforms as an option in their Semiconductor
Device Failure Analysis systems. INTER ACTION Corporation, Teseda’s
manufacturing partner and leading distributor of Teseda products for
Japan and Asia, will work with Hamamatsu Photonics to provide the platforms.
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Teseda Corporation Launches the V550™
Desktop silicon validation and diagnostic platform
ships to first customers
PORTLAND, OR-October 9, 2007 – Teseda Corporation, a
leading provider of comprehensive scan-based diagnostic and debug solutions
for semiconductor yield improvement, announced that it has launched
and is shipping it’s next generation desktop validation and diagnostic
platform, the V550™, to key customers . The V550™ is part of a unified
system that integrates design, test, and diagnostic environments, leading
to the rapid detection and repair of failures. The V550™ now becomes
the most powerful desktop validation platform in the industry, able
to handle devices with up to 512 channels and providing more memory
per channel than any other desktop system. When driven with Teseda’s
powerful TWB™ software, it allows design teams to drastically cut validation
and diagnostic time, and FA teams to quickly pinpoint failure candidates.
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