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Scan validation, silicon
debug and failure analysis in days — not weeks
Leverages your DFT to accelerate
real-time, interactive scan validation, IC silicon debug and failure
analysis
The Teseda WorkBench™ (TWB) software exploits the full power of
your DFT
investment, enabling design, test, manufacturing and FA teams to work
together to
reduce time to production, accelerate yield learning, and maximize
profits. The TWB
operates interactively on the Teseda V5xx series desktop hardware or on
your
in-house ATE to provide fast, explicit, diagnostic information based on
the design
and DFT hierarchical information. No more deciphering pin and cycle
failure
information. Turn days of debug time into hours.
Integrated scan validation graphically
identifies problems with scan chains and scan tests for faster diagnosis
The TWB software was designed to help you realize the full potential of
the DFT
that you already use in your devices by integrating with your current
tools to perform
real-time, interactive scan validation. To speed the initial silicon
validation, the TWB
features integrated scan validation to check the integrity of the
physical scan
structures and scan patterns, speeding validation and providing accurate
failure diagnosis.
Faster, more accurate failure diagnosis
through integrated bidirectional communication with EDA scan diagnostic
tools
Inside the TWB, powerful, graphic-oriented diagnostic tools process
actual device
test results, design hierarchy and scan-chain structures from IEEE1450
Standard
Test Interface Language files generated by DFT tools from Cadence,
Mentor
Graphics, Synopsys and SynTest. The Teseda WorkBench preserves and
understands the scan structures generated by your EDA tools and
communicates
bidirectionally to instantly identify specific problems in a meaningful
context for the
fastest results so that the scan tools can diagnose failures down to
the gate level.
The net result is faster, more accurate failure diagnosis.
Click here to
request a printed Teseda WorkBench™ Datasheet.
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